The European Processor Initiative is working to achieve digital sovereignty in high-performance computing by developing European-made processors.
Almost a decade ago, the European Commission decided that a special Framework Partnership Agreement (FPA) was needed to address the idea of European-made processors. Even if it wasn’t manufactured in Europe, it was definitely designed and conceived in Europe. Even before creating a special joint venture – the EuroHPC Joint Venture – to synchronize and chart the direction of Europe’s HPC efforts, the European Commission incorporated such plans into the Horizon 2020 programme, the continent’s most extensive research and innovation funding program.
european processor initiative
A group of industry and research participants formed a consortium called the European Processor Initiative (EPI) to apply for this topic under the LEIT: ICT work program. EPI subsequently obtained an FPA and began operations under Specific Grant Agreement 1 (SGA1) in 2018. The specific challenge for this topic was to help create a world-class European high-performance computing and big data ecosystem built on two exascale computing machines that rank among the top three in the world. In addition, its goal was to “establish, maintain, and execute a strategic research and innovation roadmap to build European low-power microprocessor technology that will underpin the construction of future machines for exascale-class HPC, big data, and emerging applications.” Such processors would help “foster an HPC ecosystem that can develop new European technologies such as low-power HPC chips.”
In the current unstable geopolitical situation, Europe’s plans to work towards digital sovereignty have become an important part of the political agenda, as well as research and development efforts. According to the European Council’s conclusions of 18 April 2024, “The European Council will ensure an integrated approach across all policy areas to promote a unique European socio-economic model that increases productivity and sustainable and inclusive growth across Europe, builds robust, innovative and resilient economies, and promotes the Union’s competitive transition towards digital sovereignty in a voluntary and open manner.”
1st stage (SGA1)
The need to increase independence in all areas, especially in the digital area, is no longer just a strategic idea, but can be seen as a necessity and a priority. Thus, the first phase of EPI, SGA1, brought together 28 partners from 10 countries with strong commitments from both the research and industrial sides, who decided to do everything in their power and expertise to deliver a roadmap for this processor and for EPI as a whole.
There were hurdles in creating anything from basic building blocks, let alone a sophisticated and powerful processor, and the roadmap, of course, had to be adjusted to fit every situation, but most importantly, the biggest crisis thrown at EPI and the world’s plans: a global pandemic. The first phase of EPI concluded in 2021, clearing the way for EPI’s two main pillars: the Arm family and the RISC-V family of processors.
2nd stage (SGA2)
The second phase of EPI, EPI SGA2, began with a kick-off in January 2022 by 30 partners from 10 countries under the guidance of the now established joint venture EuroHPC JU.
The plan was to continue the development of European microprocessors and accelerators, the results of SGA 1, in order to support European technological autonomy and sovereignty in this important area.
Revolutionary developments in high-performance computing
The two main pillars carried over from EPI’s plans are the Arm processor family, developed by SiPearl, a company incubated within EPI, and the RISC-V-based European Processor (EPAC).
In November 2023, the project announced the successful manufacturing and silicon demonstration of EPAC accelerator chip version 1.5, marking a significant milestone in high performance computing.
The successful launch of EPAC 1.5 was announced as a major step in the development of the EPI common platform and demonstrated a variety of accelerators that can be integrated into future European supercomputers to efficiently address a wide range of computing problems.
In July 2025, SiPearl, a company incubated within EPI, announced that Rhea1, the most complex processor ever designed in Europe, had been sent to tapeout after closing a €130 million Series A funding round with a third and final tranche of €32 million. Expected to be available for samples in early 2026, SiPearl says it will be supported by a wide range of compilers, libraries, and tools, from traditional programming languages like C/C++, GO, and RUST to modern AI frameworks like TensorFlow and PyTorch. Rhea1 is perfectly suited for its initial target market of traditional HPC and AI inference workloads.
All these developments were done with specific and specific goals in mind. One of EuroHPC JU’s missions was to support the deployment of a world-class supercomputer built with European technology and intellectual property, a system that would ultimately enhance European research and development (R&D) and industrial development. Therefore, it became essential to incorporate EPI’s IP into European supercomputers targeting exascale. The upcoming Rhea1 will be integrated into the JUPITER supercomputer, Europe’s fastest supercomputer. The next SiPearl processor, Rhea2, has been selected as part of Europe’s newest supercomputer, Alice Recoque. Alice Recoque is based in France and will accept scalar computing partitions based on the Rhea2 processor developed by SiPearl.
As the project nears completion, an updated roadmap has been released to guide future developments and outcomes outside of the project.
Promising results from consortium partners
Along with the roadmap, the project also announced the launch of some of the results from the partners participating in the consortium. Supercomputing 25, the leading global HPC conference, was the venue for two major accomplishments from partner institutions.
First, France’s CEA-List announced the open source release of VPSim, a virtual prototyping simulator used for early joint software and hardware validation and performance studies of European HPC processors. The agency says this will enable the establishment of a community of hardware and software designers dedicated to the European HPC ecosystem, accelerating design evaluation while maintaining accuracy and the joint software and hardware validation phase of next-generation HPC and edge systems.
Next, the Zagreb-based research group announced the creation of Proactive Compute, a new spin-off from the University of Zagreb Faculty of Electrical Engineering and Computing (UNIZG-FER), and the showcase of two of its main IPs: FAUST and FEVER. FAUST is a high-performance pipeline floating point unit (FPU) IP designed for integration into RISC-V cores with vector processing capabilities, and FEVER is a UVM-based RISC-V FPU verification environment that complements FPU designs. This is a SystemVerilog DPI wrapper that integrates FEVER into the UVM scoreboard to evaluate the output of the UUT.
We expect to see more such IP from EPI consortium partners in the future as the project nears formal formal completion. In addition, EPI’s research group is expected to disseminate final results through various publications and research papers, and an exhaustive dissemination repository already lists more than 60 papers, conference proceedings, and book chapters from the project period.
Please note: This is a commercial profile
This article will also be published in the quarterly magazine issue 25.
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