Every time you ask ChatGPT a question, that request triggers a data relay race. Information comes out of memory, passes through the CPU for preprocessing, goes to the GPU for heavy calculations, and then comes back. The entire process is repeated for every word the AI generates.
The bottleneck is structural, meaning each request is routed through some of the industry’s most expensive and power-hungry chips. This inefficiency is exactly what XCENA, a startup with offices in South Korea and the United States, is trying to solve. The four-year-old startup has designed a chip that brings computing capabilities much closer to DRAM, a high-speed, short-term memory chip that stores data that a processor is actively using. This allows routine data operations to be processed close to memory without costly round trips between CPU, GPU, and memory.
If it works at scale, the cost implications of AI infrastructure can be significant, which largely explains investor enthusiasm for the company. In fact, XCENA raised $135 million in Series B at a valuation of $570 million, bringing its total funding to $185 million.
XCENA CEO Jin Kim co-founded the startup in 2022 with CTO Dohoon Kim and CPO Harry Joo-hyun Kim, veterans of Samsung and SK Hynix, the memory giants that supply the chips that power NVIDIA’s GPUs. “CPUs and GPUs have both gotten smarter over the decades, but memory has never gotten smarter. XCENA wants to change that,” Jin Kim said in an interview with TechCrunch. “Recent increases in memory prices and related stocks indicate a broader shift in AI infrastructure toward memory-centric architectures,” he added. (This month, the three companies that dominate the global memory chip market, Samsung, SK Hynix, and Micron, each surpassed $1 trillion in valuation for the first time.)
XCENA is betting its business on the hypothesis that “inference is not just a computing problem, but increasingly a memory scaling problem,” Kim said.
XCENA’s chip, MX1, connects to the CPU through a Compute Express Link (CXL), essentially a dedicated express lane between the processor and memory, and processes data before it leaves the memory module. This brings compute to data, not the other way around. The company claims that what previously required 10 servers could now be done on just one.
“While GPUs are great at matrix multiplication (the complex calculations behind AI model training), much of the surrounding data orchestration still occurs on the CPU, such as preprocessing, KV cache management (a system that saves previous conversation context so the model doesn’t have to reprocess it), and data caching. Our chip handles these tasks directly within the memory module itself,” Kim said.
Demand for memory solutions has been surging since the second half of last year, and the company believes the timing is working in its favor.
Talks are in the early stages with several global memory vendors, which Kim declined to name. The company’s ideal customers are hyperscalers that spend tens of billions of dollars annually on AI infrastructure, and even small improvements in memory efficiency can lead to hundreds of millions of dollars in savings.
MX1 is still a prototype. Mass-produced chips are expected to be shipped from Samsung’s foundry lines by the end of 2026, and the company expects to generate revenue starting in 2027.
As neural processing unit (NPU) manufacturers race to take on Nvidia for training workloads, XCENA targets the memory-intensive layers underneath.
XCENA’s closest competitors include Astera Labs and Marvell, both Nasdaq-listed companies working on next-generation memory connectivity. Marvell is already a large, established company operating in the same space, Kim said, adding that the differentiating factor ultimately comes down to intellectual property. “We have thousands of cores,” Kim said. Based on public specifications, Marvell’s approach relies on a comparatively small number of general-purpose cores.
These cores are built on RISC-V, an open source chip design blueprint, and are specifically optimized for data processing, with each core intentionally kept small and efficient. Beyond the core itself, XCENA designs its own internal memory hierarchy, interconnect bus, and DRAM controller. This is the level of vertical integration that most chip companies, including their larger rivals, typically outsource.
Seoul-based VC firms Atinum and IMM Investment co-led the Series B round along with Corstone Asia and existing investors SBI Investment and Mirae Asset Capital. The company has more than 90 staff in offices in Pangyo, a technology hub on the outskirts of Seoul, and Sunnyvale, and is in talks with overseas investors to raise additional funding.
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