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Home » European Chip Law Design Enablement Team
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European Chip Law Design Enablement Team

By April 1, 2026No Comments8 Mins Read
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VUO-IC is the Finnish gateway to realizing complex SoCs.

Europe’s ambition to strengthen the semiconductor and electronics value chain is clearly expressed through the European Chip Act. Beyond major investments in manufacturing capacity, pilot lines, and research infrastructure, the Chip Act recognizes the more subtle but equally important challenge of turning ideas, architectures, and system concepts into functional devices on silicon.

For many companies in Europe, especially small and medium-sized enterprises, deep tech startups and system houses, the main bottleneck is not creativity, but access to design execution capabilities. Advanced SoC development, mixed-signal integration, RF, photonics, and emerging more-than-Moore technologies require specialized workflows, reusable IP, experienced teams, and early access to prototyping paths. Building this functionality on your own takes time and capital, and often takes focus away from what’s important to your business.

To address this gap, the Chip Act introduced a Design Enablement Team (DET) as part of the broader European Chip Design Platform (EuroCDP). DET serves as a structured, application-oriented entry point into the European semiconductor ecosystem. Their role is not to replace commercial design firms or academic research, but to connect users to the actual execution of designs, reduce friction between organizations, and significantly shorten the path from concept to demonstrator.

Within this European network, VUO-IC represents Finland’s national design enablement team, bringing together universities, research and technology organizations, and commercial design firms into a single, coordinated delivery model.

What Design Enablement Teams Actually Do

At its core, DET is built on the pragmatic principle of enabling users to deliver chips, not just designs. This distinguishes DET from advisory services, funding vehicles, or purely academic support structures.

Design enablement teams typically do the following:

Provides a single point of entry for users with chip-related ambitions Assess technical feasibility and design scope early Connect users to the right mix of design, IP, and infrastructure resources Support execution through traceable workflows Learn from the beginning to plan your route to prototype and first silicon

EuroCDP=European Chip Design Platform, CCC=Chip Competence Center, ENCCC=European Network of Chip Competence Centers, OSAT=Outsourced Assembly and Test, PCT=Platform Coordination Team, DET=Design Enablement Team, WBG Wide Bandgap, CMOS=Complementary Metal Oxide Semiconductor. Transistor technology used in almost all modern chips, RTO = Research Technology Organization

Importantly, DET is structured to work across organizational boundaries. They translate high-level policy objectives, such as European technological sovereignty, into concrete case-based support for companies that need to build hardware products under real-world commercial constraints.

VUO-IC: Finnish Design Enablement Team

VUO-IC is Finland’s EuroCDP design enablement team designed to help users deliver real chips, from system architecture and design implementation to prototypes and first silicon learnings, through a tailored service model that combines university-scale SoC capabilities, industrial design execution, and access to national prototyping.

What differentiates VUO-IC within the European DET environment is its ability to support the delivery of complex digital SoCs. Rather than focusing solely on small demonstrators or isolated IP blocks, VUO-IC is structured to support large system-level designs where complexity is often the main barrier to progress.

This capability is backed by the University of Tampere and provides a production-grade design environment and workflow suitable for complex SoCs. In addition to tools, universities provide SoC templates, reusable building blocks, and low-level software know-how. These elements are often overlooked, but are essential to avoid a “ground-up” approach to advanced design. In practice, this can significantly reduce the time required to reach your first functional demonstrator.

Industrial-grade execution is provided by CoreHW and VLSI Solution, two well-established design companies in Finland. CoreHW combines deep RF and mixed-signal expertise with a large validated IP base, and its VLSI solutions contribute to full-stack ASIC delivery experience from design to manufacturing, proven by long commercial performance and high-volume shipments. Their involvement ensures that the designs developed within VUO-IC match actual manufacturing and commercialization requirements from the beginning.

VTT complements this foundation with advanced RTO capabilities in RF and mmWave technologies, photonics, quantum and cryogenic CMOS. VTT also plays an important role as an interface to the prototyping infrastructure, ensuring that emerging and cross-domain technologies can be integrated into viable chip development paths.

Coordination and orchestration is provided by Chip Fusion, which manages admissions, case routing, and delivery monitoring. Through its leading role in Finland’s semiconductor coordination structure, Chip Fusion connects VUO-IC to the broader national ecosystem and ensures that users do not have to navigate a complex institutional environment on their own.

A service model built for execution

VUO-IC operates through a structured, case-based service model rather than open-ended consulting. This is an important difference. Users engage in defined service steps throughout the chip lifecycle, from initial feasibility assessments to tapeout preparation and prototype planning.

© Shutterstock/spainter_vfx

It all starts with one front door, managed by Chip Fusion. Each case is prioritized and routed to the appropriate execution team with clear ownership, preventing projects from getting bogged down across organizations. Delivery follows a documented workflow (scoping, activation, delivery, and termination). There, assumptions, constraints, and decisions are explicitly captured and handed down.

A feature of the VUO-IC model is that the prototype path is planned early. If the user is targeting silicon, considerations related to MPW access, packaging, testing, interfacing, and bring-up are considered from the beginning rather than after the design is complete. This reduces late-stage surprises and increases the likelihood that a “design done” will translate into a device running on silicon.

If additional infrastructure is required, such as pilot lines, specialized packaging or testing, or domain-specific expertise, VUO-IC will coordinate access through the consortium and the broader Finnish ecosystem, providing users with a tailored path rather than fragmented contacts.

Why this matters to businesses

VUO-IC offers more than just technical support, it provides a reliable shortcut to the European electronics value chain.

First, it lowers the barrier to tackling complex chip development. Companies no longer need to assemble complete SoC functionality in-house before taking the first step. By leveraging existing templates, IP, workflows, and an experienced team, you can focus on differentiation and the value of your systems rather than building infrastructure.

Second, it bridges the gap between research and industrialization. With universities, RTOs, and commercial design firms working as one delivery team, projects are less likely to fall into the common traps of being “too academic for industry” or “too fast for robustness.”

Third, it enables innovation in the mixed technology area. Many future products, whether wireless, sensing, photonics, or quantum-adjacent systems, will not fit neatly into a single technology silo. VUO-IC’s ability to span digital SoC, RF, mmWave, photonics, and More-than-Moore technologies within one design enablement team is especially valuable in this context.

Finally, participation in VUO-IC brings companies directly into the European design and prototyping flow in line with the Chip Act. This visibility and integration is essential if companies want to become meaningful contributors to Europe’s electronics ecosystem rather than peripheral technology providers.

Aiming for an integral role in Europe’s future value chains

The Design Enablement Team represents a shift in the way Europe approaches semiconductor competitiveness: from isolated excellence to collaborative capability building. VUO-IC shows how this concept can be implemented at the national level without fragmentation, duplication, and excessive bureaucracy.

VUO-IC combines a production-grade academic environment, proven industry execution, advanced RTO capabilities, and structured orchestration to transform policy intent into practical realization. For Finnish companies, this provides a concrete path from idea to functional device on silicon. For Europe, the connective tissue between design, prototyping and future manufacturing is strengthened.

As the European electronics value chain evolves towards greater complexity, heterogeneity and system integration, such models will become increasingly central. In this sense, VUO-IC is not only a Finnish design enablement team, but also a blueprint for how a smaller, highly specialized ecosystem can play a decisive role in the future of semiconductors in Europe.

VUO-IC value proposition to users

A proven shortcut to complex SoCs: You don’t have to build everything from scratch. We provide SoC templates, reusable blocks, and practical know-how (including low-level SW interfaces) that typically take years to assemble.

Industrial-grade execution, not academic instruction: Two commercial design firms complement the university/RTO’s strengths with their experience in delivering verified IP libraries and shipping chips.

One team across Digital + RF + More-than-Moore: Digital SoC, RF/mixed-signal, RF/mmWave, photonics, and quantum-related paths are covered within one DET, so mixed-domain projects aren’t fragmented.

Clear route to prototype and first silicon learning: Plan MPW, packaging, and launch as part of the same delivery flow. Therefore, “complete design” becomes “working silicon.”

Single ingestion, clear routing, and traceable delivery: Chip Fusion runs a practical triage and orchestration model so you know who’s doing what, what needs to happen next, and how progress is tracked.

partner:

Please note: This is a commercial profile

This article will also be published in the quarterly magazine issue 25.


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