As the EPI completes its second stage, it speaks to some of its project partners to find out more about the processors being developed by the project
European Processor Initiative, a project of 27 partners from ten countries working on developing a low-power processor that will power European exascale supercomputers, finished last month, after two stages of a special Framework Partnership Agreement. Even though the official period of project duration is over, project stream leaders are still steering considerable IPs of consortium partners’ work towards final results.
It started out as an initiative to help bring about European digital sovereignty after winning the FPA call from the largest funding programme for research and innovation in 2017, Horizon 2020. EPI consortium members aimed to develop a processor that would power supercomputers achieving exascale: a high-performance, low-power processor implementing vector instructions and specific accelerators with high-bandwidth memory access. The second stage started in 2022, with two processor families being developed under EPI: an Arm-based General-Purpose Processor (Rhea GPP) and the European accelerator (EPAC).
The first one, Rhea1, which is coming back from tapeout – was developed by a company incubated within EPI – SiPearl. It was only natural that SiPearl’s engineers and specialists were to lead this part of work within EPI. In this article, we talk to stream leaders of both processor families, to share their insight into how this work was approached. The article also interviews one of EPI’s industry representatives, CEO and founder of Semidynamics.
Rhea General-Purpose Processor
Céline Scetbun, SiPearl’s Project Manager, and EPI’s stream leader, gave us insight into how Rhea1 was developed and what SiPearl gained from being a part of EPI consortium.
Tell us about the history of SiPearl, and what role EPI had in enabling this start?
SiPearl and EPI are closely intertwined. In 2014, the EU decided to address its weak position in high-performance computing (HPC) compute elements with funding mechanisms through the Horizon 2020 programme. Concurrently, Philippe Notton, drawing on more than 20 years of experience in the semiconductor industry, saw the opportunity to address this gap in non-European hardware for strategic applications in data centres and supercomputers. Europe moved on to create the EuroHPC JU, which defined a long-term roadmap for HPC and AI in Europe. Meanwhile, Philippe joined ATOS with the intention of heading development of an EU HPC General Purpose Processor (seed funded by the EPI), either as part of ATOS or as a spinout/independent company.
Launched in 2018, the European Processor Initiative has seeded a rich research consortium, gathering industrial and academic stakeholders, leading to the creation of companies like SiPearl. SiPearl was founded in 2019 through EPI seed funding to become the industrial team tasked with transforming research into tangible products in the form of sovereign EU general purpose high-performance low-power microprocessors.
What are the current developments in the company?
We can take this question in two ways: what are the things we are working on in parallel for Rhea1, and what are the developments we are working on across generations of processors.
For Rhea1, we are working closely with Bull which, in addition to being an investor, is a key SiPearl partner advising on all things system and developing a Rhea1 motherboard for their BullSequana system, funded through the EPI, that will be deployed in the first European Exascale supercomputer, JUPITER.
Beyond the hardware design of Rhea1, our performance team is actively working on the benchmarks and performance optimisations, with the help of virtual platforms and an emulator platform that we purchased and deployed; our SW and firmware teams are porting and developing software, and upstreaming patches and solutions for open-source code such as the Linux operating system.
Indeed, in large part thanks to DG-CNCT, EuroHPC JU and the EPI, Europe has a rich and growing network of industry and academic stakeholders working to develop all kinds of IP across the continent that will enhance domain-specific applications.
Regarding the development of our product roadmap beyond Rhea1 (Athena1, as well as our second and third-generation product families), we cover this later in this text.
What is the status of Rhea1?
Rhea1 taped out in June 2025 and the first samples will arrive in SiPearl in the coming weeks. Tapeout marked the conclusion of the design, development, and intensive testing phase conducted within EPI project and marked a major milestone for European technological sovereignty in supercomputing.
Since the tapeout, SiPearl has continued the testing and preparation of the Rhea1 bring-up on several fronts. First by completing development of the Seine Reference server to host, test, validate and demonstrate Rhea1.
In parallel, SiPearl has continued software development to ensure readiness of the full stack and tools to test the very first samples.
SiPearl faced delay in the manufacturing at packaging level due to preferential allocations at TSMC for larger customers, but we have made the most of this time by running automated tests on the wafers – we have run 80% of the chip structural test coverage with success, which will help us in prioritising our bring-up tests. Packaging assembly is now almost finalised, and the team is now all set to get started on the bring-up when the chip arrives.
Are there any details you can share about the developmental roadmap for Rhea1 and Athena?
Beyond Rhea1, at the request of sovereign private and public entities in defence, government, and aerospace, we will derive a variant of Rhea1, called Athena1, which removes the high bandwidth memory to create a more compact EU sovereign CPU for these key markets.
SiPearl is also working on our second generation of products, spearheaded by Rhea2, where the architecture shifts from the monolithic die of Rhea1 to a chiplet-based solution. Rhea2 will be used in the Alice Recoque Supercomputer and will also be the vehicle for SiPearl to enter the CSP processor market.
Finally, SiPearl is architecting our third generation of products that will further exploit chiplet and advanced packaging technology. We are partnering with accelerator providers to pioneer EU common standards for compute elements aggregated from multiple EU companies and institutes.
Why is this important for European sovereignty?
We have seen the effects of holes in our supply chains with the COVID-19 pandemic, and now more importantly with geopolitics, leading to technology embargos and ITAR restrictions. Beyond source of supply, the concern over backdoors and kills switches in EU technology sourced from other geographies is now a real threat. With the development of sovereign high-performance processors, Europe is addressing these concerns and, in addition, is developing/enhancing an ecosystem for IP, advanced packaging, open-source SW, photonics, networking, and a multitude of other technologies.
If you can, please compare Rhea1 and Athena in terms of usage of HBM, and future chiplet approach
Athena1 is a bespoke version of Rhea1, designed to meet the specific requirements of the government, defence, and aerospace markets in terms of computing power, security, and environmental constraints (thermal, vibration, radiation, etc.). Simplistically, Athena1 removes the HBM used in Rhea1 and is housed in a more robust package. More specifically, using the base die of Rhea1 but housed in a new Ball Grid Array package, Athena1 will provide SKUs of 16, 32, 48, 64, or 80 Arm Neoverse V1 compute cores. Packaging will initially take place in Taiwan, before being entrusted to a network of European specialists with the goal of establishing a new supply chain in Europe.
EPAC Accelerator
The development of the second processor family in EPI, European accelerator (EPAC), was led by stream leader from Barcelona Super Computing, Filippo Mantovani, who we have had the opportunity to talk to about spearheading such a complex project. Fillipo shared his experiences about the work itself, but also about coordinating such a big number of consortium partners.
How was it leading heterogeneous teams? Can you share your view of challenges or opportunities?
One of the main challenges – and also the biggest opportunity – was working with highly heterogeneous teams, from industry to academia. Despite very different backgrounds and perspectives, we managed to converge toward a common goal. In a way, building real hardware naturally aligns people: at some point, everything has to fit together and work.
Another key aspect was the length of the knowledge chain we covered. We went from architectural design to implementation, validation, FPGA and ASIC flows, all the way up to compilers and software. Bringing all these domains together, even just finding a common language, is complex – but also extremely rewarding when it results in a working chip able to accelerate real scientific codes.
Long vectors: An architectural problem or a way to explore?
Long vectors are an efficient way to scale performance by exploiting data-level parallelism over large datasets. This approach fits naturally with HPC workloads, but also with emerging domains where throughput and energy efficiency are critical. It also works well in combination with modern memory systems, helping to tolerate data movement latency.
Conceptually, this is not far from approaches seen in today’s paradigms, such as NVIDIA’s CUDA Tiles. While the implementation differs, the underlying idea is similar: applying the same operations to large chunks of data to maximise efficiency. In this sense, RISC-V vector extensions provide a flexible and future-proof foundation.
Continuity of RISC-V in EU: Does it work?
Yes, continuity exists, and it is essential to create real impact. EPI has built a solid foundation in Europe in terms of IP, know-how, and ecosystem, which is now being reused and extended not only in follow-up projects but also by partners for their business based in Europe.
Independently of whether the EPI chip targets the most advanced technology node, the key achievement is that Europe now has the capability to cover the full stack required to design complex processors. Several partners also developed IP that is now silicon-proven, which is a major step forward: it means these components are not just concepts, but are ready to be reused in future products.
Part of these experiences from various EPAC collaborators are now described in a paper that will be presented at the next Computing Frontiers conference – taking place on May 19-21 2026, in Catania, Italy.
New value for European companies
Creating new value for Europe also means giving companies in the consortium an opportunity to grow their business and create new IP. In the RISC-V processor family of EPI, Semidynamics company from Barcelona undertook the development of RISC-V CPU IP. Details about the cooperation and their work were given here by Roger Espasa, CEO and Founder.
What was Semidynamics’ role in EPI? Was there a role EPI had in helping Semidynamics develop its RISC-V IP?
Semidynamics played a key role in the European Processor Initiative by contributing the development of its RISC-V CPU IP, which became one of the foundational building blocks within the project. Our work focused on advancing a high-performance, energy-efficient RISC-V core tailored for demanding computing environments, integrating our own technology with that of the other partners.
EPI provided an important framework and support to accelerate the development of this IP. In particular, it enabled us to validate our core design through silicon prototypes and FPGA-based platforms, which are essential steps in increasing the technology readiness level (TRL) of any processor architecture. These activities helped us move from concept and design stages toward more mature, validated implementations.
Beyond the technical aspects, EPI also gave us the opportunity to collaborate with a wide ecosystem of European partners. This collaboration enriched our development process and allowed us to align our technology with broader European goals in high-performance computing and digital sovereignty. Overall, EPI played a meaningful role in helping us strengthen the foundations of our RISC-V portfolio.
Can you share something about the new AI HW solution in your company?
At Semidynamics, we are currently developing a new generation of AI processors, accelerator chips, and full-rack systems built around our advanced RISC-V architecture. These products and technologies are designed specifically to accelerate AI and HPC workloads. A key differentiator of our approach is the tight integration between compute, memory, and data movement. Our architecture is designed to efficiently handle large datasets and complex AI models, which are increasingly central to modern applications, from data centres to edge computing.
We have recently announced the tapeout of a new system in an advanced 3nm technology node, developed outside of the EPI project. At the same time, the work carried out within EPI has contributed to the evolution of our processor technology, helping us mature key building blocks and accelerate our overall development roadmap.
We are also targeting leading-edge semiconductor technology nodes, which allow us to push performance and energy efficiency to the next level. This positions our processors to compete globally in areas such as AI inference, scientific computing, and large-scale data processing.
Importantly, the work we carried out in developing our IP, partly supported by initiatives like EPI, has enabled us to take significant steps forward in our roadmap. We are now transitioning from pure IP development to full product realisation and commercial deployment, which is a major milestone for the company.
Please share some insight about the latest successful investment into Semidynamics
Semidynamics has recently announced a strategic investment from SK Hynix, one of the world’s leading memory manufacturers. This investment reflects a shared conviction that memory architecture, not compute alone, will define the economics of next-generation AI inference, where cost per token is the metric that matters.
The investment enables us to further strengthen our engineering capabilities, accelerate product development, and move forward with advanced silicon implementations. It also reinforces our ability to engage with customers and partners worldwide, supporting the deployment of our technology in real-world applications.
More broadly, this milestone highlights the growing importance of system-level innovation in AI, particularly the tight coupling between compute and memory. It also represents a strong validation of our architectural approach and a key step in consolidating our transition from IP development to delivering complete, high-performance computing solutions.
What would you consider a positive effect of EPI on your company and development of your business?
One of the most positive effects of EPI has been its role in enabling us to advance our core technology and strengthen our position in the semiconductor ecosystem. The project provided valuable support for developing and validating our RISC-V IP, which today serves as the backbone of our product portfolio.
Through EPI, we were able to take meaningful steps along our development path, from early-stage IP creation to more mature, validated designs. This progress has been instrumental in preparing us for commercial opportunities and in building confidence among customers and investors.
Additionally, EPI fostered collaboration across a diverse set of European partners, which helped us better understand system-level challenges and integration requirements. This has had a lasting impact on how we design our products today, with a stronger focus on real-world applications and scalability.
Finally, participation in EPI has contributed to increasing our visibility within the European and global semiconductor landscape. It has positioned Semidynamics as a key player in the RISC-V and AI chip and full system space, opening new opportunities for partnerships and business development.
In summary, EPI has been an important steppingstone in our journey, supporting both our technological evolution and our transition toward commercially viable products.
Please Note: This is a Commercial Profile
This article will feature in our upcoming HPC Special Focus Publication.
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