Sebastian Wood, Principal Scientist at the National Physical Laboratory (NPL), emphasizes the importance of measurement standards in accelerating semiconductor technology.
The artificial intelligence (AI) revolution is hitting a physical wall. As AI models become exponentially more powerful, the hardware supporting them is also struggling to keep up. The semiconductor industry, driven by the miniaturization of silicon chips, is now facing fundamental limits in power consumption, thermal management, and data transfer speeds. Hardware innovation was once the key to enabling breakthrough advances, but as technology becomes more complex, pioneering further is becoming increasingly difficult. Measurement has become a key driver to continue driving innovation.
This challenge has sparked a wave of innovation. New materials and architectures are rapidly emerging in the lab and across industry to fill the gaps. 3D stacked chiplets, high-bandwidth interconnects, and neuromorphic designs that mimic the human brain are no longer just theoretical concepts. Even emerging technologies such as 2D materials as transistor channels and diamond heat sinks are increasingly seen as essential next steps.
However, as the industry moves beyond traditional silicon architectures, it faces critical issues that are often overlooked. That means the measurement science needed to validate these technologies at scale often doesn’t yet exist. You can’t build what you can’t measure, and you can’t scale what you can’t reliably test.
Hardware bottlenecks and silicon limitations
The demand for high-performance computing, driven by the transition to AI and 6G communications, is pushing current chip architectures to their limits. As leading research centers like Imec point out, the roadmap for silicon scaling is moving toward the atomic dimension, where the material’s properties begin to fluctuate.
There are three limiting factors that create this bottleneck. First, there are physical limits to the number of transistors that can be placed on a single 2D chip. The industry is addressing this problem by moving to 3D stacking, but this requires new processes to align hundreds of layers with nanometer precision, which poses a major metrology challenge. Second, this incredible density generates enormous amounts of heat, requiring new thermal management techniques and materials such as diamond to prevent the chips from melting.
Finally, there is what is known as the “memory wall.” Processor speed has increased much faster than the ability to transfer data from individual memory chips. This data transfer rate is currently the main limiting factor for performance. High-bandwidth memory and tighter chip integration will bring incremental benefits, but the long-term solution lies in new concepts. Optical communication is faster than electrical wires, but integrating optical communication between memory and processing chips requires the integration of different materials to realize the dream of co-packaged optical elements (CPOs). Additionally, neuromorphic computing, which aims to mimic the behavior of biological neurons, has the potential to be significantly more energy efficient than digital silicon computing for AI applications. However, the choice of materials and architecture is still speculative at this point.
Close the missing functionality gap with measurement
As the industry explores these new materials, architectures, and 3D structures, the most urgent missing capability is the metrology needed to test and validate them. New materials require new technology. Small features require high-resolution methods. For example, 3D stacks require tools that can see through the entire structure. This has already facilitated the use of X-ray technology in measurements. Additionally, to enable the use of new materials such as 2D transition metal dichalcogenides and diamond, they must be able to be grown at wafer scale, posing fundamental challenges when it comes to scale-up.
Currently, these processes do not exist and are expensive to develop. An important function for industry is to evaluate the performance and reliability of final products. As device performance improves and specifications become more stringent, more robust measurement capabilities become essential.
Britain’s opportunity: From R&D leadership to global standards
The UK is in a unique position to solve this problem. Although the country is not a high-volume silicon chip manufacturer, its greatest strength lies in its world-leading R&D ecosystem, supported by leading universities and a cluster of global semiconductor companies that base their research here.
The UK can leverage this research and development strength in certain high-value areas to maintain its position as a world leader in this area. Our research leadership in compound semiconductors and silicon-based photonics expands the possibilities of co-packaged optics. Our world-leading expertise in diamond growth directly addresses critical thermal management issues. And our deep research into 2D materials and neuromorphic devices could provide the foundation for the next two generations of AI computing.
The key is to connect this innovation to global markets. As UK innovators seek to gain traction, they will rely on metrics to demonstrate the performance of their products. Testing your technology against recognized standards can help you de-risk your investment and secure your customers. This is where “pre-standards” research, the process by which national laboratories work with industry to develop these standards, becomes a commercial necessity. This provides early access to best practices and ensures that standards are in place to support the market when it is ready.
As detailed in our recent report on semiconductor metrology priorities in the UK, providing innovators with access to cutting-edge metrology can reduce time to market for new products and deliver significant benefits. By leading the development of these new measurements and standards, the UK can shape global markets, give innovators access to international supply chains and turn research and development leadership into tangible economic benefits.
This article will be featured in an upcoming High Performance Computing Special Focus publication.
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